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// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
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// to the terms and conditions of the Altera Program License 
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// Generated by Quartus II 64-Bit Version 14.1 (Build Build 186 12/03/2014)
// Created on Wed Apr 12 15:44:08 2017

PLL_CORE PLL_CORE_inst
(
	.inclk0(inclk0_sig) ,	// input  inclk0_sig
	.c0(c0_sig) ,	// output  c0_sig
	.c1(c1_sig) 	// output  c1_sig
);

